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never stop thinking. hyb39s512400at(l) HYB39S512800AT(l) hyb39s512160at(l) 512-mbit synchronous dram sdram data sheet, rev. 1.3, march 2003 memory products
edition 2004-03 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb39s512400at(l) HYB39S512800AT(l) hyb39s512160at(l) 512-mbit synchronous dram sdram data sheet, rev. 1.3, march 2003 memory products
template: mp_a4_v2.2_2003-10-07.fm hyb 39s512[40/80/16]0at(l) revision history: rev. 1.3 2004-03 page subjects (major changes since last revision) 18 removed extended mode register previous version: rev. 1.22 2003-09 page subjects (major changes since last revision) 17 corrected mode register definition in chapter 3 all various layout and editorial changes we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 1.3, 2004-03 hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 signal pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 package p-tsopii-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 operation definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.1 read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.2 dqm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.3 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5.4 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram data sheet 6 rev. 1.3, 2004-03 table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3 signal pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4 truth table: operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6 bank selection by address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10 i dd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11 i dd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
data sheet 7 rev. 1.3, 2004-03 hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram figure 1 pinoutp-tsopii-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 block diagram for 128m 4 sdram ( 13 / 12 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 block diagram for 64m 8 sdram ( 13 / 11 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 block diagram for 32m 16 sdram ( 13 / 10 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 measurement conditions for t ac and t oh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6 package outlines p-tsopii-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 list of figures
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram overview data sheet 8 rev. 1.3, 2004-03 10082003-l1gd-pvi5 1 overview 1.1 features ? fully synchronous to positive clock edge 0 to 70 c operating temperature four banks controlled by ba0 & ba1 programmable cas latency: 2 & 3 programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8 and full page multiple burst read with single write operation automatic and controlled precharge command data mask for read / write control ( 4, 8) data mask for byte control ( 16) auto refresh (cbr) and self refresh power down and clock suspend mode 8192 refresh cycles / 64 ms (7,8 s) random column address every clk ( 1-n rule) single 3.3 v 0.3 v power supply lvttl interface versions plastic packages: p-tsopii-54 400mil width (x4, x8, x16) 1.2 description the hyb 39s512[40/80/16]0at(l) are four bank synchronous dram?s organized as 4 banks 32mbit 4, 4 banks 16mbit 8 and 4 banks 8mbit 16 respectively. these synchronous devices achieve high speed data transfer rates for cas -latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with infineon?s advanced 0.14 m 512mbit dram process technology. the device is designed to comply with all industry standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operates with a single 3.3 v 0.3 v power supply. all 512mbit components are housed in p-tsopii-54 packages. table 1 performance part number speed code ? 7 ? 7.5 ? 8unit speed grade pc133 2?2?2 pc133 3?3?3 pc100 2?2?2 ? max. clock frequency @cl3 f ck 143 133 125 mhz t ck3 77.58ns t ac3 5.4 5.4 6 ns @cl2 t ck2 7.5 10 10 ns t ac2 5.4 6 6 ns
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram overview data sheet 9 rev. 1.3, 2004-03 10082003-l1gd-pvi5 table 2 ordering information type speed grade package description hyb 39s512400at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b 32m 4 sdram hyb 39s512400at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b 32m 4 sdram hyb 39s512400at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b 32m 4 sdram hyb 39s512800at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b 16m 8 sdram hyb 39s512800at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b 16m 8 sdram hyb 39s512800at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b 16m 8 sdram hyb 39s512160at-7 pc133-222-520 p-tsop-54-2 (400mil) 143mhz 4b 8m 16 sdram hyb 39s512160at-7.5 pc133-333-520 p-tsop-54-2 (400mil) 133mhz 4b 8m 16 sdram hyb 39s512160at-8 pc100-222-620 p-tsop-54-2 (400mil) 125mhz 4b 8m 16 sdram hyb 39s512xx0atl pc100-xxx-620 p-tsop-54-2 (400mil) low power versions (on request)
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 10 rev. 1.3, 2004-03 10082003-l1gd-pvi5 2 pin configuration 2.1 signal pin description table 3 signal pin description pin type signal polarity function clk input pulse positive edge clock input the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high clock enable activates the clk signal when high and deactivates the clk signal when low, thereby initiating either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low chip select cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras cas we input pulse active low command signals when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a12 input level ? address inputs during a bank activate command cycle, a0-a12 define the row address (ra0-ra12) when sampled at the rising clock edge. during a read or write command cycle, a0-an define the column address (ca0-can) when sampled at the rising clock edge. can depends upon the sdram organization: 64m x4 sdram can = ca9, ca11 (page length = 2048 bits) 32m x8 sdram can = ca9 (page length = 1024 bits) 16m x16 sdram can = ca8 (page length = 512 bits) in addition to the column address, a10 (= ap) is used to invoke the autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (= ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? bank select bank select inputs. bank address inputs selects which of the four banks a command applies to. dqx input output level ? data input/output data input/output pins operate in the same manner as on edo or fpm drams.
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 11 rev. 1.3, 2004-03 10082003-l1gd-pvi5 2.2 package p-tsopii-54 figure 1 pinoutp-tsopii-54 dqm ldqm udqm input pulse active high data mask the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input is present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. v dd v ss supply ? ? power and ground power and ground for the input buffers and the core logic (3.3 v) v ddq v ssq supply ? ? power and ground for dqs isolated power supply and ground for the output buffers to provide improved noise immunity. nc ? ? ? not connected no internal electrical connection is present. table 3 signal pin description pin type signal polarity function vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 18 19 20 21 22 23 24 25 26 27 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 vdd 128m x 4 64m x 8 32m x 16 tsopii-54 (400 mil x 875 mil, 0.8 mm pitch)
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 12 rev. 1.3, 2004-03 10082003-l1gd-pvi5 2.3 block diagrams figure 2 block diagram for 128m 4 sdram ( 13 / 12 / 2 addressing) memory array bank 1 x4bit memory array bank 2 x4bit memory array bank 3 x4bit column address counter row decoder memory array bank 0 x4bit column decoder sense amplifier &i(o)bus row decoder sen se amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer r efresh c ounter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap,a11,a12 , ba0, ba1 colum n addresses row addresses input buffer o utpu t b uffer dq0 - dq3 control logic & timing generator clk cke cs ras cas we dqm column decode r colu mn decoder 8192 x4096 8192 x4096 8192 x 4096 8192 x4096
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 13 rev. 1.3, 2004-03 10082003-l1gd-pvi5 figure 3 block diagram for 64m 8 sdram ( 13 / 11 / 2 addressing) memory array bank 1 x8bit memory array bank 2 x8bit memory array bank 3 x8bit column address counter row decoder memory array bank 0 x8bit column decoder sense amplifier &i(o)bus row decoder sen se amplifier & i(o) bus row decoder row decoder column decoder sense amplifier & i(o) bus row address buffer column address buffer r efresh c ounter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap,a11 ba0, ba1 colum n addresses row addresses input buffer o utpu t b uffer dq0 - dq7 control logic & timing generator clk cke cs ras cas we dqm column decode r colu mn decoder 8192 x2048 8192 x2048 8192 x 2048 8192 x2048
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram pin configuration data sheet 14 rev. 1.3, 2004-03 10082003-l1gd-pvi5 figure 4 block diagram for 32m 16 sdram ( 13 / 10 / 2 addressing) memory array bank 1 x16bit memory array bank 2 x16bit memory array bank 3 x16bit column address counter row decoder memory array bank 0 x16bit column decoder sense amplifier & i(o) bus row decoder sense amplifier & i(o) bus row decoder row decoder column decoder sense amplifie r&i(o)bus row address buffer column address buffer refresh counter sense amplifier & i(o) bus a0 - a12, ba0, ba1 a0 - a9, ap, ba0, ba1 column addresses row addresses input buffer output buffer dq0 - dq15 control logic & timing generator clk cke cs ras cas we dqmu dqml column decoder column decoder x 1024 x 1024 x 1024 x 1024 8192 8192 8192
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 15 rev. 1.3, 2004-03 10082003-l1gd-pvi5 3 functional description 3.1 operation definition all sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. table 4 truth table: operation command operation devics state cke n-1 1)2) 1) v = valid, x = don?t care, l = low level, h = high level 2) cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. cke n 1)2) dqm 1)2) ba0 ba1 1)2) ap= a10 1)2) addr 1)2) cs 1)2) ras 1)2) cas 1)2) we 1)2) bank active idle 3) 3) this is the state of the banks designated by ba0, ba1 signals. hxxv v vllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3) hxxv l vlhll write with autopre- charge active 3) hxxv h vlhll read active 3) hxxv l vlhlh read with autopre- charge active 3) hxxv h vlhlh mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) lhxx x xhxxx lh h x clock suspend entry active l h x x x x x x x x power down entry (precharge or active standby) idle hlxx x x hx x x active 4) 4) power down mode can not be entered in a burst cycle. when this command asserted in the burst mode cycle device is in clock suspend mode. lh h h clock suspend exit active l h x x x x x x x x power down exit any (power down) lhxx x xhxxx lh h l data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 16 rev. 1.3, 2004-03 10082003-l1gd-pvi5 3.2 initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed v dd + 0.3 v on any of the input pins or v dd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. 3.3 mode register definition the mode register designates the operation mode at the read or write cycle. this register is divided into four fields. first, a burst length field which sets the length of the burst, second, an addressing selection bit which programs the column access sequence in a burst cycle (interleaved or sequential). third, a cas latency field to set the access time at clock cycle. fourth, an operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. after the initial power up, the mode set operation must be done before any activate command. any content of the mode register can be altered by re- executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table.
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 17 rev. 1.3, 2004-03 10082003-l1gd-pvi5 mr mode register definition (ba[1:0] = 00 b ) ba1 ba0 a12 a13 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 mode cl bt bl reg. addr w w w w field bits type description bl [2:0] w burst length number of sequential bits per dq related to one read/write command note: all other bit combinations are reserved 000 1 001 2 010 4 011 8 111 full page bt 3w burst type see table 5 for internal address sequence of low order address bits. 0 sequential 1 interleaved cl [6:4] w cas latency number of full clocks from read command to first data valid window. note: all other bit combinations are reserved 010 2 011 3 operating mode [13:7] w operating mode note: all other bit combinations are reserved. 0 burst read / burst write 1 burst read / single write
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 18 rev. 1.3, 2004-03 10082003-l1gd-pvi5 3.3.1 burst length note: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 3.4 commands refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for either refresh mode. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a positive clock transition. the mode restores word line after the refresh and no external precharge command is necessary. a minimum t rc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self refresh mode is available. the mode restores the word lines after ras , cas , and cke are low and we is high at a positive clock transition. all external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one t rc delay is required prior to any access command. table 5 burst length and sequence burst length starting column address o rder of accesses within a burst a2 a1 a0 type = sequential type = interleaved 2 0 0-1 0?1 1 1?0 1?0 4 0 0 0?1?2?3 0?1?2?3 0 1 1?2?3?0 1?0?3?2 1 0 2?3?0?1 2?3?0?1 1 1 3?0?1?2 3?2?1?0 8 0 0 0 0?1?2?3?4?5?6?7 0?1?2?3?4?5?6?7 0 0 1 1?2?3?4?5?6?7?0 1?0?3?2?5?4?7?6 0 1 0 2?3?4?5?6?7?0?1 2?3?0?1?6?7?4?5 0 1 1 3?4?5?6?7?0?1?2 3?2?1?0?7?6?5?4 1 0 0 4?5?6?7?0?1?2?3 4?5?6?7?0?1?2?3 1 0 1 5?6?7?0?1?2?3?4 5?4?7?6?1?0?3?2 1 1 0 6?7?0?1?2?3?4?5 6?7?4?5?2?3?0?1 1 1 1 7?0?1?2?3?4?5?6 7?6?5?4?3?2?1?0 full page n n n cn, cn+1, cn+2 .... not supported
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 19 rev. 1.3, 2004-03 10082003-l1gd-pvi5 auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. if ca10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation a time delay equal to t wr (?write recovery time?) after the last data in. a burst operation with auto-precharge may only be interrupted by a burst start to another bank. it must not be interrupted by a precharge or a burst stop command. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr (?write recovery time?) of 2 clocks minimum from the last data out to apply the precharge command. burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. 3.5 operations 3.5.1 read and write when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is ?2?, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. table 6 bank selection by address bits a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xxall banks
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram functional description data sheet 20 rev. 1.3, 2004-03 10082003-l1gd-pvi5 full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organization and column addressing. full page burst operation does not self terminate once the burst length has been reached. in other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated using another command. similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be performed between different pages. 3.5.2 dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). 3.5.3 suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). 3.5.4 power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay ( t rp ) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device can?t remain in power down mode longer than the refresh period ( t ref ) of the device. exit from this mode is performed by taking cke ?high?. one clock delay is required for power down mode entry and exit.
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 21 rev. 1.3, 2004-03 10082003-l1gd-pvi5 4 electrical characteristics 4.1 operating conditions attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. table 7 absolute maximum ratings parameter symbol values unit note/ test condition min. max. voltage on i/o pins relative to v ss v in , v out ?1.0 +4.6 v power supply voltage v dd , v ddq ?1.0 +4.6 v operating temperature t a 0+70 c storage temperature range t stg ?55 +150 c power dissipation per sdram component p d ?1 w data out current (short circuit) i out ?50ma table 8 input and output capacitances 1) 1) t a = 0 to 70 c; v dd, v ddq = 3.3 v 0.3 v, f = 1 mhz parameter symbol values 2) 2) capacitance values are shown for tsop-54 packages. capacitance values for tfbga packages are lower by 0.5 pf unit min. max. input capacitance: ck, ck c i1 2.5 3.5 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i2 2.5 3.8 pf input / output capacitance (dq) c i0 4.0 6.0 pf
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 22 rev. 1.3, 2004-03 10082003-l1gd-pvi5 table 9 dc characteristics 1) 1) t a =0 to 70 c parameter symbol values unit note/ test condition min. max. supply voltage v dd 3.0 3.6 v 2) 2) all voltages are referenced to v ss i/o supply voltage v ddq 3.0 3.6 v 2) input high voltage v ih 2.0 v ddq +0.3 v 2)3) 3) v ih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3 v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3 v. pulse width measured at 50% points with amplitude measured peak to dc reference. input low voltage v il ?0.3 0.8 v 2)3) output high voltage ( i out =?4.0 ma) v oh 2.4 ? v 2) output low voltage ( i out = 4.0 ma) v ol ?0.4 v 2) input leakage current, any input (0 v < v in < v dd , all other inputs = 0 v) i il ?5 5 a output leakage current (dqs are disabled, 0 v < v out < v ddq ) i ol ? 55 a table 10 i dd conditions parameter symbol operating current single bank, burst length 4 i o =0 ma i dd1 precharge standby current in power down mode cs = v ih,min ; cke v il,max i dd2p precharge standby current in non-power down mode cs = v ih(min.) , cke v ih(min.) i dd2n active power-down standby current one bank active state(max. 4 banks) cs = v ih(min.) ,cke v ih(min.) i dd3n active standby current one bank active state (max. 4 banks) cs = v ih(min.) , cke v il(max.) i dd3p burst operating current read command cycling i dd4 auto refresh current auto refresh command cycling t rfc = t rfc(min.) i dd5 self refresh current self refresh mode, cke=0.2v, t ck =infinity 16 i dd6
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 23 rev. 1.3, 2004-03 10082003-l1gd-pvi5 table 11 i dd specifications symbol ? 7 ? 7.5 ? 8 unit note/test condition 1) 1) t a = 0 to 70 c; v ss = 0 v, v dd , v ddq = +3.3 v 0.3 v typ. max. typ. max. typ. max. i dd1 131 145 123 145 95 110 ma 2) 3) 2) these parameters depend on the cycle rate. all values are measured at 133 mhz for ?-7? and ?-7.5? and at 100 mhz for ?-8? components with the outputs open. input signals are changed once during t ck . 3) these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the v ddq current is excluded. i dd2p 0.6 3 0.6 3 0.6 3 ma 2) i dd2n 25 31 23 31 19 25 ma 2) i dd3n 27 35 26 35 21 30 ma 2) i dd3p 242424ma 2) i dd4 102 123 97 123 79 100 ma 2) 3) i dd5 270 300 255 300 240 270 ma t rfc = t rfc(min.) 4) 4) t rfc = t rfc(min.) ?burst refresh?. i dd6 2.1 4 2.1 4 2.1 4 ma standard
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 24 rev. 1.3, 2004-03 10082003-l1gd-pvi5 4.2 ac characteristics table 12 ac characteristics 1)2)3) parameter symbol ? 7 ? 7.5 ? 8 unit notes pc133-222 pc133-333 pc100-222 min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 7 7.5 ? ? 7.5 10 ? ? 8 10 ? ? ns ns clock frequency cas latency = 3 cas latency = 2 t ck ? ? 143 133 ? ? 133 100 ? ? 125 100 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 3)4)5) clock high pulse width t ch 2.5 ? 2.5 ? 3 ? ns clock low pulse width t cl 2.5 ? 2.5 ? 3 ? ns transition time t t 0.3 1.2 0.3 1.2 0.5 10 ns setup and hold times input setup time t is 1.5 ? 1.5 ? 2 ? ns 6) input hold time t ih 0.8 ? 0.8 ? 1 ? ns 6) cke setup time t ck 1.5 ? 1.5 ? 2 ? ns 6) cke hold time t ckh 0.8 ? 0.8 ? 1 ? ns 6) mode register set-up to active delay t rsc 2?2?2?clk power down mode entry time t sb 0707.508ns common parameters row to column delay time t rcd 15 ? 20 ? 20 ? ns 7) row precharge time t rp 15 ? 20 ? 20 ? ns 7) row active time t ras 37 100k 45 100k 48 100k ns 7) row cycle time t rc 60 ? 67 ? 70 ? ns 7) row cycle time during auto refresh t rfc 63 67 70 ns activate(a) to activate(b) command period t rrd 14 ? 15 ? 16 ? ns 7) cas (a) to cas (b) command period t ccd 1?1?1?clk refresh cycle refresh period (8192 cycles) t ref ?64?64?64ms self refresh exit time t srex 1?1?1 clk
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 25 rev. 1.3, 2004-03 10082003-l1gd-pvi5 read cycle data out hold time t oh 3?3?3?ns 3)6) data out to low impedance time t lz 1?1?0?ns data out to high impedance time t hz 373738ns dqm data out disable latency t dqz ?2?2?2clk write cycle last data input to precharge (write without autoprecharge) t wr 14 ? 15 ? 16 ? ns 8) last data input to activate (write with auto precharge) t dal(min.) ( t wr / t ck ) + ( t rp / t ck )clk 9) dqm write mask latency t dqw 0?0?0?clk 1) t a = 0 to 70 c; v ss = 0 v, v dd , v ddq = 3.3 v 0.3 v, t t = 1 ns 2) for proper power-up see the operation section of this data sheet. 3) ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with an input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 4) if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 5) if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 6) access time from clock tac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time toh is 1.8 ns for pc133 components with no termination and 0 pf load. 7) this parameter determines the minimum required number of clock cycles as follows: the required number of clock cycles is given by the value of the specified parameter divided by the period of the clock. non-integer values must be rounded up to the next greater integer value. 8) it is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without auto-precharge. one clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater or equal the specified t wr value, where t ck is equal to the actual system clock time. 9) when a write command with autoprecharge has been issued, a time of t dal(min.) has be fullfilled before the next activate command can be applied. for each of the terms, if not already an integer, round up to the next highest integer. tck is equal to the actual system clock time. table 12 ac characteristics 1)2)3) parameter symbol ? 7 ? 7.5 ? 8 unit notes pc133-222 pc133-333 pc100-222 min. max. min. max. min. max.
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram electrical characteristics data sheet 26 rev. 1.3, 2004-03 10082003-l1gd-pvi5 figure 5 measurement conditions for t ac and t oh 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v in p u t is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hyb 39s512[40/80/16]0at(l) 512-mbit synchronous dram package outlines data sheet 27 rev. 1.3, 2004-03 10082003-l1gd-pvi5 5 package outlines figure 6 package outlines p-tsopii-54 gpx09039 22.22 0.13 1) 127 54 28 0.35 +0.1 -0.05 0.1 1 0.1 10.16 0.13 0.2 11.76 0.1 0.5 does not include plastic or metal protrusion of 0.15 max per side 1) 54x 0.05 0.05 0.15 -0.03 +0.06 15? 5? 15? 5? 6 max 2.5 max 2) 3) does not include plastic protrusion of 0.25 max per side 2) does not include dambar protrusion of 0.13 max per side 3) index marking 0.8 20.8 26x 0.8 = 0.2 m 54x plastic package p-tsopii-54 (400 mil, 0.8 mm lead pitch) thin small outline package, smd
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